The present invention generally relates to compound semiconductor field effect transistors and, more particularly, to compound semiconductor field effect transistors suitable for high output power.
Field effect transistors using compound semiconductor, hereinafter referred to as compound FETs, have been used as a high frequency transistor in the field of mobile communication. Generally, the compound FET is implemented in the form of MESFET (Metal Semiconductor FET) or in the form of MISFET (Metal Semiconductor Insulator FET). This is because, unlike the case of using silicon, it is impossible to prepare a MOSFET since it is extremely difficult to form, on a surface of a compound semiconductor substrate, an oxide film capable of providing a semiconductor-insulator junction which is stable and whose surface order is low. Accordingly, whereas a silicon FET is formed on a conductive substrate, a MESFET or MISFET is formed by the use of an insulating compound semiconductor substrate or semi-insulating compound semiconductor substrate. Hereinafter, throughout the specification, by the term xe2x80x9csemi-insulatingxe2x80x9d is meant at lest xe2x80x9csemi-insulationxe2x80x9d and the term includes also xe2x80x9cinsulationxe2x80x9d.
The way of fabricating a compound FET is divided, in terms of how its semiconductor layer is formed, roughly into two types, namely a method which employs ion implantation and another which employs epitaxial growth. The epitaxial growth process has several advantages over the ion implantation process. One of the advantage is that it is possible to form semiconductor layers high in impurity concentration and thin in film thickness, thereby making it possible to provide high-gain compound FETs. Another advantage is that, in MISFET, such a structure that the gate is not brought into direct contact with an active (operational) layer can be formed by using a high-purity intrinsic compound semiconductor layer (e.g., a non-dope aluminum gallium arsenic (i-AlGaAs)) as a gate contact layer, thereby allowing the realization of FETs capable of high current drive while at the same time securing a high breakdown voltage with no sacrifice in breakdown voltage, which is difficult for the ion implantation process to achieve. Owing to these advantages over the ion implantation process, there has been more need for epitaxially-grown compound FETs capable of serving as a high-frequency high output power FET for use in, for example, portable telephone power amplifiers.
Based on the phenomenon that the width of a depletion layer that is formed in an active layer (which is also called an electron transit layer or a channel) formed over a semi-insulating compound semiconductor substrate varies according to the level of the gate voltage, the compound FET controls a source-drain current. However, since the active layer is formed on the semi-insulating substrate, this will give rise to a problem of causing the compound FET to vary in its current-voltage characteristic (the I-V characteristic) when a high electric field is internally created.
The cause of such FET I-V characteristic variation will be discussed below.
Upon creation of a high electric field in the inside of a compound FET, electrons are accelerated by the high electric field to come to have high energy. When such a high energy electron collides with the lattice, this creates an electron-hole pair (an ion), which phenomenon is called xe2x80x9cimpact ionizationxe2x80x9d. Typically, the active layer is an n-type compound semiconductor layer and, of the created electron-hole pair, the electron merges with a carrier of the active layer and then flows to the high potential side, that is, towards the drain. On the other hand, the created holes are injected into the substrate. As a result, the potential of the substrate increases and the injected holes are accumulated around under a gate of the substrate. Due to the influence of the holes, the width of a depletion layer in the active layer varies, and there occurs a change in the FET current-voltage characteristic.
FIGS. 15A and 15B each show a band structure for a gate electrode 76, an active layer (n-GaAs) 74, and a semi-insulating substrate (i-GaAs) 72 in an n-type gallium arsenic (GaAs)-including MESFET. FIG. 15A shows a state immediately after an electron-hole pair has been created by impact ionization. FIG. 15B shows an approximately stable state after a definite period of time has elapsed since the electron-hole pair creation. As can be seen from FIG. 15A, of the electron-hole pairs created in the active layer 74, the holes are liable to accumulate under the gate electrode along the potential surface of VB (valence band) or enter into the substrate 72. Upon injection of the holes into the substrate 72, the electric potential of the semi-insulating substrate 72, which is in agreement with a Fermi level (EF) in FIG. 15A, increases by an amount of xcex94Vsub as shown in FIG. 15B. As a result, the width of the depletion layer 75 that is formed between the active layer 74 and the substrate 72 becomes narrower than that of FIG. 15A. Such a reduction in the depletion layer width caused by the holes being injected into the semi-insulating substrate 72 is similar to the phenomenon that the depletion layer width is reduced when there is an increase in the p-type impurity concentration in a P/N contact. A reduction in the width of a depletion layer below the gate electrode 76 means that the region that contributes to conduction within the active layer 74 will increase, so that there is an increase in the drain current even when both the gate voltage and the drain voltage are constant. Such a phenomenon appears as a kink (bent) 78 in the I-V curve, as shown in FIG. 16.
Referring now to FIGS. 16A and 16B, there are graphically shown I-V curves for different gate voltages of the compound FET, wherein the abscissa indicates the drain voltage and the ordinate the drain current. Whereas FIG. 16A shows an ideal I-V curve, FIG. 16B shows a conventional FET I-V curve. As described above, if the depletion layer width is narrowed by holes and the region that contributes to conduction within the active layer 74 increases, this results in a sudden increase in the drain current. As a result, the I-V curve bends, in other words the kink 78 is produced. Accordingly, in the vicinity of such a kink in the I-V curve, it is impossible to obtain a desired drain current even when performing control of the gate and drain voltages. Moreover, as the drain current varies, generally the FET optimum matching impedance varies considerably. This means that a FET that suffers a kink cannot be served as a high frequency power amplification FET the important requirement for which is impedance matching.
In order to obtain high-frequency high output power FETs, the realization of a high breakdown voltage (i.e., a high gate breakdown voltage) has been demanded, together with the controlling of the creation of kinks in the I-V curve.
An example of the kink creation control in MESFET is disclosed by M. Nagaoka et. al., in their paper entitled xe2x80x9cHigh efficiency, low adjacent channel leakage 2-V operation GaAs power MESFET amplifier for 1.9 GHz digital cordless phone systemxe2x80x9d, IEEE MTT-S Digest, pp.1323-1326, 1997. Referring to FIG. 17, there is schematically illustrated a MESFET 1200 disclosed in the document.
The MESFET 1200 has a semi-insulating substrate 82 formed of i-GaAs, an n-type active layer 86 formed by implantation of ions into the semi-insulating substrate 82, and three different electrodes (i.e., a source electrode 87, a drain electrode 88, and a gate electrode 89) which are formed on their respective regions over the n-type active layer 86. The n-type active layer 86 has an n-type compound semiconductor layer 86c formed below the gate electrode 89, an n-type compound semiconductor layer 86b formed adjacent to each side of the n-type compound semiconductor layer 86c, and an n+ semiconductor layer 86a for the establishment of ohmic contact with each of the source electrode 87c and the drain electrode 88. Further, p-type compound semiconductor layers 84s and 84d are formed by ion implantation below the n+ semiconductor layers 86a formed under the source electrode 87 and under the drain electrode 88, respectively, in other words they are formed on the substrate side.
A part of holes created by impact ionization taking place within the n-type active layer 86 passes through the gate electrode 89 and is emitted to outside the compound FET 1200 in the form of gate current. On the other hand, the remaining holes are not accumulated in the semi-insulating substrate 82, but they are accumulated in the p-type compound semiconductor layer 84s on the source side (the reason is that no hole is accumulated in the p-type compound semiconductor layer 84d on the drain side because a positive voltage is applied to a drain electrode of the FET having an n-type active layer).
Moreover, even when holes are accumulated in the p-type compound semiconductor layer 84s, the width of a depletion layer that is formed between the p-type compound semiconductor layer 84s and the n+ semiconductor layer 86a will hardly vary because the n-type impurity concentration of the n+ semiconductor layer 86a formed just above the p-type compound semiconductor layer 84s is sufficiently high. As a result, the semi-insulating substrate 82 hardly varies in electric potential. Accordingly, even when holes are created in the compound FET 1200, the width of a depletion layer that is formed between the n-type active layer 86 and the semi-insulating substrate 82 is not varied, so that no kink will occur in the I-V curve.
However, the MESFET disclosed in the foregoing document is prepared by an ion implantation process, so that, as discussed above, it is difficult to make high current drive capability compatible with high breakdown voltage. This prior art MESFET is therefore not suitable for high output power at high frequencies.
FIG. 18 schematically shows in cross section a structure of a typical MISFET 1300. The MISFET 1300 has an epitaxially-grown aluminum gallium arsenic (AlGaAs)/GaAs heterojunction. The MISFET 1300 has a semi-insulating substrate 92 (GaAs), a buffer layer 92a (i-GaAs), an n-type compound semiconductor layer 94 (n-GaAs) which is an active layer, a semi-insulating compound semiconductor layer 95 (i-Al0.2Ga0.8As) which functions as an insulating layer, and a contact layer 96 (n-GaAs), these layers being formed in that order on the semi-insulating substrate 92. Both a source electrode 97 and a drain electrode 98 are formed on the contact layer 96, while a gate electrode 99 is located above the semi-insulating compound semiconductor layer 95.
Upon creation of holes in the active layer 94 of the MISFET 1300 by impact ionization, like the MESFET, a part of the holes is injected into the semi-insulating substrate 92 (which includes the buffer layer 92a which is semi-insulating). This causes the potential of the substrate 92 to increase, as a result of which the width of a depletion layer between the n-type compound semiconductor layer 94 and the semi-insulating substrate 92 narrows and there is an increase in the drain current. In addition to this, in the MISFET 1300, a part of the holes is accumulated in the surface of the semi-insulating compound semiconductor layer 95, as a result of which the width of a surface depletion layer that is formed between the source and gate narrows and there is an increase in the drain current. This state will be described by making reference to FIG. 19. FIG. 19 depicts a band structure under the gate electrode 99 of the MISFET 1300. A part of holes that have been created within the n-GaAs layer 94 by impact ionization travels along the potential surface of VB (valence band) and is accumulated at a heterojunction interface between the i-AlGaAs layer 95 and the n-GaAs layer 94. Further, a part of the accumulated holes moves past the heterojunction and is accumulated in the surface of the semi-insulating compound semiconductor layer 95 (i.e., the interface with the gate electrode 99). As a result, the width of a surface depletion layer that is formed between the source and gate narrows and there is an increase in the drain current.
As described above, there have been proposed a way of controlling the variation in compound FET I-V characteristic (the occurrence of kinks); however, such proposals are limited to MESFETs fabricated by ion implantation.
Unfortunately, there has not yet been developed any control method of controlling the variation in the compound FET I-V characteristic of compound FETs (particularly MISFETs) fabricated by epitaxial growth having an expectant future of application.
The present invention was made with a view to providing a solution to the above-described problem. Accordingly, an object of the present invention is to provide a compound FET capable of achieving high output power in a high frequency region and a method for the fabrication of such a compound FET.
The present invention provides a compound semiconductor field effect transistor comprising (a) a compound semiconductor substrate having a semi-insulating surface, (b) a charge absorption layer including a compound semiconductor layer of a first conductive type formed in a part of the compound semiconductor substrate, (c) a semiconductor laminated structure including at least an active layer having a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed, (d) a source electrode formed on the semiconductor laminated structure located above the charge absorption layer, the source electrode being electrically connected to the charge absorption layer, (e) a drain electrode formed on the semiconductor laminated structure located above the region where the charge absorption layer is not formed, and (f) a gate electrode formed between the source electrode and the drain electrode, whereby the foregoing object can be achieved.
The present invention provides an arrangement in which the compound semiconductor field effect transistor further comprises (a) an additional electrode formed on the semiconductor laminated structure, (b) an ohmic contact region extending from the additional electrode to the charge absorption layer through semiconductor laminated structure, and (c) a connection electrode electrically connecting the additional electrode and the source electrode.
The present invention provides an arrangement in which the compound semiconductor field effect transistor further comprises (a) a contact hole formed in a part of the semiconductor laminated structure, the contact hole extending to the charge absorption layer, (b) an additional electrode electrically connected to the charge absorption layer in the contact hole, and (c) a connection electrode electrically connecting the additional electrode and the source electrode.
The present invention provides an arrangement in which (a) the compound semiconductor field effect transistor further comprises a further compound semiconductor layer of the second conductive type formed on the charge absorption layer and (b) the semiconductor laminated structure is formed so as to cover the charge absorption layer, the further compound semiconductor layer of the second conductive type, and the region where the charge absorption layer is not formed.
The present invention provides a method for the fabrication of a compound semiconductor field effect transistor comprising the steps of (i) providing a compound semiconductor substrate having a semi-insulating surface, (ii) forming, in a part of the compound semiconductor substrate, a charge absorption layer including a compound semiconductor layer of a first conductive type, (iii) epitaxially growing a semiconductor laminated structure including at least an active layer having a compound semiconductor layer of a second conductive type, so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed, (iv) forming a source electrode electrically connected to the charge absorption layer on the semiconductor laminated structure located above the charge absorption layer, (v) forming a drain electrode on the semiconductor laminated structure located above the region where the charge absorption layer is not formed, and (vi) forming a gate electrode between the source electrode and the drain electrode, whereby the foregoing object can be achieved.
The present invention provides an arrangement in which the charge absorption layer formation step includes selectively implanting impurity ions of the first conductive type into a predetermined region of the compound semiconductor substrate.
The present invention provides an arrangement in which the charge absorption layer formation step includes (i) epitaxially growing the compound semiconductor layer of the first conductive type on the semi-insulating surface of the compound semiconductor substrate, and (ii) patterning the compound semiconductor layer of the first conductive type into a predetermined shape.
The present invention provides an arrangement in which (a) the semiconductor laminated structure formation step includes (i) epitaxially growing the active layer, (ii) epitaxially growing an intrinsic compound semiconductor layer on the active layer, and (iii) epitaxially growing on the intrinsic compound semiconductor layer a contact layer having a compound semiconductor layer of the second conductive type, (b) the drain electrode formation step includes (i) forming a drain electrode on the contact layer, and (ii) forming an ohmic contact region between the drain electrode and the contact layer, and (c) the gate electrode formation step includes (i) removing a part of the contact layer so as to expose a part of the intrinsic compound semiconductor layer and (ii) forming a gate electrode on the exposed part of the intrinsic compound semiconductor layer.
The present invention provides an arrangement in which the source electrode formation step includes thermally diffusing a metallic material of the source electrode to form an ohmic contact region extending from the source electrode to the charge absorption layer through the semiconductor laminated structure.
The present invention provides an arrangement in which the source electrode formation step includes (i) forming on the semiconductor laminated structure an additional electrode of a metallic material, (ii) thermally diffusing the additional electrode metallic material to form an ohmic contact region extending from the additional electrode to the charge absorption layer through the semiconductor laminated structure, and (iii) forming a connection electrode electrically connecting the additional electrode and the source electrode.
The present invention provides an arrangement in which the source electrode formation step includes (i) forming, in a part of the semiconductor laminated structure, a contact hole extending to the charge absorption layer, (ii) forming an additional electrode being in direct contact with the charge absorption layer in the contact hole, (iii) forming a source electrode on the semiconductor laminated structure, and (iv) forming a connection electrode electrically connecting the additional electrode and the source electrode.
The present invention provides an arrangement in which (a) the compound semiconductor field effect transistor fabrication method further comprises (i) forming on the charge absorption layer a further compound semiconductor layer of the second conductive type and (ii) patterning the second compound semiconductor layer of the second conductive type into the same shape as the charge absorption layer and (b) the semiconductor laminated structure formation step is a step of forming the semiconductor laminated structure so as to cover the charge absorption layer, the patterned second compound semiconductor layer of the further conductive layer, and the region where the charge absorption layer is not formed.
The present invention provides an arrangement in which (a) the compound semiconductor field effect transistor fabrication method further comprises (i) forming on the charge absorption layer a second compound semiconductor layer of the further conductive type and (ii) patterning the second compound semiconductor layer of the second conductive type into the same shape as the charge absorption layer, (b) the semiconductor laminated structure formation step is a step of forming the semiconductor laminated structure so as to cover the charge absorption layer, the patterned further compound semiconductor layer of the second conductive layer, and the region where the charge absorption layer is not formed, and (c) the source electrode formation step includes (i) forming, in a part of the semiconductor laminated structure, a contact hole extending to the compound semiconductor layer of the first conductive type, (ii) forming an additional electrode being in direct contact with the compound semiconductor layer of the first conductive type in the contact hole, (iii) forming a source electrode on the semiconductor laminated structure, and (iv) forming a connection electrode electrically connecting the additional electrode and the source electrode.